| 0.3 slot packets | 24.Reserved | ||
| 1.5 slot packets | 25.Enhanced Data Rate ACL 2 Mbps mode | ||
| 2.Encryption | 26.Enhanced Data Rate ACL 3Mbps mode | ||
| 3.Slot offset | 27.Enhanced inquiry scan | ||
| 4.Timing accuracy | 28.Interlaced inquiry scan | ||
| 5.Role switch | 29.Interlaced page scan | ||
| 6.Hold mode | 30.RSSI with inquiry results | ||
| 7.Sniff mode | 31.Extended SCO link (EV3 packets) | ||
| 8.Park state | 32.EV4 packets | ||
| 9.Power control requests | 33.EV5 packets | ||
| 10.Channel quality driven data rate (CQDDR) | 34.Reserved | ||
| 11.SCO link | 35.AFH capable slave | ||
| 12.HV2 packets | 36.AFH classification slave | ||
| 13.HV3 packets | 37.Reserved | ||
| 14.μ-law log synchronous data | 38.Reserved | ||
| 15.A-law log synchronous data | 39.3-slot Enhanced Data Rate ACL packets | ||
| 16.CVSD synchronous data | 40.5-slot Enhanced Data Rate ACL packets | ||
| 17.Paging parameter negotiation | 41.reserved | ||
| 18.Power control | 42.reserved | ||
| 19.Transparent synchronous data | 43.AFH capable master | ||
| 20.Flow control lag (least significant bit) | 44.AFH classification master | ||
| 21.Flow control lag (middle bit) | 45.Enhanced Data Rate eSCO 2 Mbps mode | ||
| 22.Flow control lag (most significant bit) | 46.Enhanced Data Rate eSCO 3 Mbps mode | ||
| 23.Broadcast encryption | 47.3-slot Enhanced Data Rate eSCO packets |